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IR11682S
Application Information and Additional Details
State Diagram
POWER ON
Gate Inactive
UVLO MODE
VCC < VCCon
Gate Inactive
I CC = I CC START
VCC > VCCon
& V DS >V TH3
VCC < VCCuvlo
NORMAL
Gate Active
Gate PW ≥ MOT
Cycle by Cycle MOT Check Enabled
V DS >V TH1 @ MOT
V DS <V TH1 @ MOT
MOT PROTECTION
MODE
Gate Output Disabled
UVLO Mode:
The IC is in the UVLO mode when the VCC pin voltage is below VCCUVLO. The UVLO mode is accessible
from any other state of operation. In the UVLO state, most of the internal circuitry is unbiased and the IC
draws a quiescent current of ICCSTART.
The IC remains in the UVLO condition until the voltage on the VCC pin exceeds the VCC turn on threshold
voltage, VCC ON.
Normal Mode:
Once Vcc exceeds the UVLO voltage, the IC is ready to go into Normal mode. The GATE outputs are
activated when the VDS sensed on the MOSFET crosses VTH3. This function will prevent the GATE to turn-
on towards the end of a switching cycle and prevent reverse current in MOT time. In Normal mode the gate
drivers are operating and the IC will draw a maximum of ICC from the supply voltage source.
MOT Protection Mode
If the secondary current conduction time is shorter than the MOT (Minimum On Time) time, the next driver
output is disabled. This function can avoid reverse current that occurs when the system works at very light/no
load conditions and reduce system standby power consumption by disabling GATE outputs. The IC
automatically goes back to normal operation mode once the load increases to a level and the secondary
current conduction time is longer than MOT.
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